Trellis code detector and decoder

ABSTRACT

The present invention is to reduce the maximum magnetization reversal interval of a trellis code. A trellis diagram for the trellis code takes into consideration a constraint condition on the DSV of a code and an inter-symbol-interference for three bits. The minimum squared Euclidean distance is 4. When a non-interleaving encoder and a non-de-interleaving code detector are constructed using the trellis diagram, the maximum magnetization reversal interval of a trellis code to be used is reduced to half of that in a known case while having the error rate and circuit size approximately equal to those in the known case. The trellis diagram has a basic repeating unit for two bits. In the actual apparatus, the trellis diagram is repeatedly used. The present invention is applicable to a read/write apparatus.

TECHNICAL FIELD

The present invention relates to trellis code detectors and decodingapparatuses, and, for example, relates to a trellis code detector anddecoding apparatus capable of greatly reducing the maximum run-length ofa code for use in detecting a trellis code that is used to reduce theerror rate of a digital transmission signal in magnetic read/writeapparatuses including digital video cassette recorders or hard diskdrives for computers and the like, various read/write apparatusesincluding magneto-optical read/write apparatuses such as magneto-opticaldisk drives, and various communications apparatuses.

BACKGROUND ART

In various recent read/write apparatuses and communications apparatuses,research and development has been actively conducted on trellis codedmodulation (TCM), which is one effective means for reducing the codeerror rate of digital transmission signals. TCM is a scheme thatcombines convolutional coding or block coding, both of which take intoconsideration the characteristics of channels, with decoding such asViterbi decoding using a trellis diagram based on a state transitiondiagram of a code. A coding rule is used by a code detector to calculatethe likelihood. By increasing the minimum Euclidean distance dminbetween trellis code sequences used by the code detector, the error rateof digital transmission signals is reduced.

FIG. 1 is a block diagram of a digital signal processing circuit in ageneral read/write apparatus.

An encoder 1 encodes rate m:n input data where m represents the data bitlength of unencoded data (prior to encoding) and n represents the databit length of encoded data (subsequent to encoding). A D/A converter 2converts the input write code from a digital signal into an analogsignal, that is, a write rectangular wave. A read/write unit 3 includesa magnetic head, an optical pickup, a control circuit for controllingthe driving of the magnetic head and the optical pickup, and the like.The read/write unit 3 writes the write wave input from the D/A converter2 in a recording medium (not shown).

The read/write unit 3 reads a signal recorded in the recording mediumand outputs an analog read wave to an analog equalizer 4. The analogequalizer 4 equalizes the read wave input from the read/write unit 3 topredetermined target equalization characteristics. An A/D converter 5converts the input analog equalized wave into an equalized signal, thatis, a digital read signal. Recently, maximum likelihood detectors aregenerally used to serve as a code detector 6. The code detector 6converts the input digital read signal, that is, the equalized signal,into a code. In other words, the code detector 6 detects a code. Adecoder 7 decodes the input detected code at a rate of n:m, generatesoutput data, and outputs the output data.

The A/D converter 5 includes a phase locked loop (PLL). As the PLL, ahybrid digital PLL that only performs phase error detection by a digitalunit or a full-digital PLL that performs both phase error detection andsignal synchronization by a digital unit may be used.

When equalization by the analog equalizer 4 is insufficient, a digitalequalizer may be provided between the A/D converter 5 and the codedetector 6.

In code detection using TCM, a coding rule used by the encoder 1 is usedby the code detector 6.

Recently, TCPR (trellis Coded Partial Response) that combines TCM andpartial response equalization has been extensively discussed to serve assignal processing for magnetic read/write apparatuses. TCPR is atechnique for increasing the free squared Euclidean distance by anencoding method and consequently improving the S/N (Signal/Noise:signal-to-noise ratio), whereby high-density recording is made possible.Hereinafter the free squared Euclidean distance may also be referred toas the free distance.

The free distance refers to the minimum Euclidean distance between twodifferent paths, both of which originate in a common state and end in acommon state on a trellis diagram representing an output sequence of apartial response channel. The trellis diagram is also referred to as adetection trellis. Viterbi detection is performed on the basis of thetrellis diagram. The start state and the end state need not be the same.

One known type of trellis code for use in TCPR modulation is an MSN(Matched Spectral Null) code in which a null point of a code spectrum onthe frequency axis matches a null point of a signal spectrum that hasbeen partial-response-equalized by limiting a running digital sum (RDS)or an alternating digital sum (ADS) of a code sequence or both RDS andADS to finite values.

The characteristics of the MSN code and a code detection method thereforare described in detail by, for example, R. Karabed and P. Siegel in“Matched Spectral-Null Codes for Partial-Response Channels,” IEEE Trans.on Info. Theory, vol. 37, No. 3., PP. 818–815, May 1991.

RDS is computed by allocating +1 and −1 to symbols “1” and “0” of a codeand computing the sum of symbols from the start point, that is, theinitial point, of the code sequence. A code whose digital sum variation(DSV) of RDS is limited to a finite value has a spectral null at a DCcomponent of the power spectrum of the code.

Such a code is known as an MSN code for a dicode channel having 1-Dequalization characteristics wherein D is a delay element representing aone-bit delay on the frequency axis. A code whose DSV is limited to afinite value is not limited to the MSN code and is generally referred toas a DC free code. In this case, DSV is two or greater.

For example, the minimum squared Euclidean distance d_(min) ² of a codedetection trellis for the dicode channel is 2. By using a code detectiontrellis combining the DSV limitation rule and 1-D equalizationcharacteristics, if 2<DVS, equation (1) holds true; if 2=DSV, equation(2) holds true:d_(min) ²=4  (1)d_(min) ²=6  (2)

When d_(uncoded) represents the minimum Euclidean distance of unencodeddata prior to encoding by the code detector 6, and d_(coded) representsthe minimum Euclidean distance of encoded data subsequent to encoding bythe code detector 6, the gain of coding by the code detector 6, that is,the coding gain, is expressed by equation (3):20 log(d_(coded)/d_(uncoded))dB  (3)

In this case, if 2<DSV, the coding gain is 3 dB; if DSV=2, the codinggain is 6 dB.

Putting the 1-D equalization into practical use without modification isdifficult because the 1-D equalization involves very large noiseamplification in the high frequency band. In many cases, obtaining asatisfactory signal-to-noise ratio is difficult.

ADS involves, in NRZ modulation, allocation of +1 or 0 to each symbol ina code sequence, multiplication of every other bit by −1, NRZ modulationof the code sequence, and computation of the sum of all symbols from thestart point. In NRZI modulation, NRZI modulation is performed on allinverted symbols, and the sum of all symbols from the start point iscomputed. A code whose A-DSV (Alternating Digital Sum Variation) of ADSis set to a finite range has a null at a Nyquist frequency component ofthe power spectrum of the code.

Such a code is known as an MSN code on a channel having equalizationcharacteristics of (1+D)^(x) (where x is a natural number). A code whoseA-DSV is set to a finite range is not limited to the MSN code and isgenerally referred to as a Nyquist free code. In this case, A-DSV is twoor greater.

(1+D)^(x) equalization is known as being capable of achieving asatisfactory signal-to-noise ratio in read/write apparatuses since noisein the high frequency band of a read signal is suppressed. (1+D)^(x)equalization in a case in which, for example, x=1, that is, 1+Dequalization, is generally referred to as PR1 (Partial Response Class-I)equalization. PR1 equalization is put into practical use in, forexample, magnetic read/write apparatuses for 3.8-mm streaming tapes and8-mm streaming tapes.

Such partial response classification was done by Kretzmer. In general,partial response classification that complies with the contents of“Generation of a Technique for Binary Data Communication” by E. R.Kretzmer, IEEE Trans. on com. Tech., pp. 67–68, February 1996 is used.

For example, the minimum squared Euclidean distance d_(min) ² of a codedetection trellis on a PR1 channel is 2. By using a code detectiontrellis combining A-DSV and PR1 equalization characteristics, if2<A-DSV, equation (4) holds true; if A-DSV=2, equation (5) holds true:d_(min) ²=4  (4)d_(min) ²=6  (5)

(1+d)^(x) equalization requires a DC component. When this equalizationis used in a magnetic read/write apparatus that does not transmit a DCcomponent, generally the DSV of a code must be limited to a finite valuein order to prevent degradation of the signal-to-noise ratio of thesystem. Generally in an optical read/write apparatus that transmits a DCcomponent, the DSV of a code must be similarly limited to a finite valuein order to stabilize the PLL and to detect a servo signal.

Codes whose DSV and A-DSV are both limited to finite values havespectral nulls at DC and Nyquist frequency points. Such codes are notlimited to MSN codes and are generally referred to as DC- andNyquist-free codes. In other words, when using MSN codes, magneticread/write apparatuses employing (1+d)^(x) equalized channels use DC-and Nyquist-free codes.

PR1 MSN codes have already been put into practice by AIT2 (AdvancedIntelligent Tape drive II) systems. AIT2 is the standard for 8-mmstreaming tape magnetic read/write apparatuses.

DC- and Nyquist-free codes are known as MSN codes for channels with(1−D)(1+D)^(x) equalization characteristics. Since (1−D)(1+D)^(x)equalization suppresses noise in both the low-frequency band and thehigh-frequency band, including DC, of a read signal, such (1−D)(1+D)^(x)equalization achieves a satisfactory signal-to-noise ratio in read/writeapparatuses, and especially in magnetic read/write apparatuses that donot transmit DC components.

In (1−D)(1+D)^(x) equalization, since x=1, that is, (1−D)(1+D), 1−D²equalization is generally referred to as PR4 (Partial Response Class-IV)equalization. The details of PR4 that has spectral nulls at both DC andNyquist frequency points are described by Lyle J. Fredrickson in “On theShannon Capacity of DC- and Nyquist-Free Code”, IEEE Transactions onInformation Theory, Vol. 37, No. 3, pp. 918–923, May 1991. PR4 hasalready been put into practice by hard disk drives, consumer digitalVCRs (Video cassette recorders), and the like.

For example, the minimum squared Euclidean distance d_(min) ² of a codedetection trellis on the PR4 channel is 2. Using a code detectiontrellis combining the DSV and A-DSV limitation rules and PR4equalization characteristics, d_(min) ² is 4 or 6, as in the case of thedicode channel.

When both the DSV and A-DSV limitation rules are reflected in the codedetection trellis, the trellis detector becomes very complicated.Observation on an every-other-bit basis of a PR4 equalized signal having1−D² equalization characteristics gives 1−D equalizationcharacteristics. Generally, a PR4 MSN code is easily constructed byinterleaving a dicode channel MSN code on a bit-by-bit (bitwise) basis,assuming that the code is distinctively detected on a bit-by-bit basis.

When the dicode channel MSN code, which is a DC free code, isinterleaved on a bit-by-bit basis, a write code is a DC- andNyquist-free code in which both DSV and A-DSV are limited. In this case,null points of the code spectrum perfectly match null points of the PR4equalization spectrum. The code is the PR4 MSN code.

In other words, the following method is generally used. When an MSN codeis used on the PR4 channel, a dicode channel MSN code in which DSV islimited to a finite value is interleaved on a bit-by-bit basis, and aresulting code is recorded on a recording medium. When reading the code,the equalized signal is de-interlieaved on a bit-by-bit basis to detectthe code.

As described above, although MSN codes obtain high coding gain, PR4codes are difficult to put into practice in actual apparatuses.

One cause of this problem is that a known method employs a low codingrate of 4/5 and that the signal-to-noise ratio is greatly degraded inthe case of a high linear recording density. Such a known method is thusinapplicable in practice. Recently, however, as disclosed in JapaneseUnexamined Patent Application Publication No. 11-186917 submitted by theinventor of the present invention and in “High-Rate Matched SpectralNull code” by M. Noda, IEEE Trans. on Magn., vol. 34, No. 4, pp.1946–1948, July 1998, this weakness is improved by technology concerningMSN codes having a high coding rate of 8/9.

Another cause of the problem of the PR4 MSN code being difficult to putinto practice is that the maximum magnetization reversal interval Tmaxis increased when the code is recorded. In the case of NRZI recording,the maximum magnetization reversal interval Tmax when the code isrecorded is the maximum length of a continuous sequence of data 0 (themaximum run-length)+1. In the case of the PR4 MSN code, the maximummagnetization reversal interval Tmax is increased since two independentdicode channel MSN codes are interleaved on a bit-by-bit basis. In otherwords, the maximum magnetization reversal interval Tmax of aninterleaved code (subsequent to interleaving) is twice as high as themaximum magnetization reversal interval Tmax of a non-interleaved code(prior to interleaving).

In the case of NRZI recording, the maximum magnetization reversalinterval Tmax is the sum of the maximum length of a continuous sequenceof data 0 (the maximum run-length) and 1. In the case of NRZ recording,the maximum magnetization reversal interval Tmax is equivalent to themaximum run-length.

For example, in magnetic reading apparatuses, a reduction in Tmax of acode has a great favorable influence on the reduction in overwrite noiseof a read signal and on PLL stabilization. Specifically, when Tmax of acode is high, information for achieving PLL synchronization is reduced,which may cause a failure.

In the case of a high Tmax, azimuth recording generates a highcross-talk from neighboring tracks, which in turn degrades the qualityof read data. As discussed above, a reduction in Tmax of a code iswidely known to help improve the performance of read/write apparatuses.

In the read/write apparatuses, especially a helical-scan tape systemusing a rotary drum, a high-pass filter is formed by a windinginductance of a rotary transformer and a winding DC resistance of awrite head. The low frequency components of a recording current waveformare cut off, and it is difficult to write a recording waveform signalwith a high Tmax on a magnetic tape.

In general read/write apparatuses, Tmax of a code to be used isgenerally designed such that approximately Tmax≦9T where T denotes theclock time interval. The above-described rate 8/9 dicode channel MSNcode has a Tmax of 7T. In contrast, when this code is interleaved on abit-by-bit basis, Tmax of the resultant code is twice as high, that is,14T. In other words, since the two independent dicode channel MSN codesare interleaved on a bit-by-bit basis, Tmax becomes very high, which isinapplicable in practice.

DISCLOSURE OF INVENTION

In view of the foregoing circumstances, when using a trellis codedetecting method for performing code detection using coding rules forlikelihood calculation, it is an object of the present invention toperform PR4 equalization without interleaving a dicode MSN code on abit-by-bit basis and to perform code detection using a trellis diagramincluding both a limitation rule of a DC component or a Nyquistcomponent of a code spectrum and an inter-symbol-interference rule forthree bits.

In view of the foregoing circumstances, when using a trellis codedetecting method for performing code detection by using a coding rulefor likelihood calculation, it is an object of the present invention toperform code detection by performing PR4 equalization of a dicodechannel MSN code without interleaving the code on a bit-by-bit basis andusing a trellis diagram including both a coding rule on a DC componentor a Nyquist component of a code spectrum and aninter-symbol-interference rule for three bits.

A trellis code detector of the present invention includes a codedetector for performing trellis code detection by applying a coding rulethat there is a spectral null at one of a DC component and a Nyquistcomponent of a code spectrum and a partial-response class-IVinter-symbol-interference rule.

The inter-symbol-interference rule may be an inter-symbol-interferencerule for three bits.

The code detector may perform code detection using a trellis diagram towhich the coding rule on the spectral null at the DC component and theinter-symbol-interference rule for three bits are applied.

The code may be a combination of codes in which the number ofconsecutive ones in a signal prior to Non Return to Zero Inverted (NRZI)modulation is limited to a finite value.

The code may be a combination of codes with a coding rate of 8/9 orgreater.

The code may be a non-interleaved code sequence.

In the code, at least one of a digital sum variation (DSV) of a runningdigital sum (RDS) and a DSV of an alternating digital sum (ADS) of acode sequence may be limited to a predetermined value n (n is an integergreater than or equal to 2). In order to generate 2n or moretransitional states, the code detector may includes ACS circuits, thenumber of which is the same as the number of states.

A trellis code detecting method of the present invention includes a codedetecting step of performing trellis code detection by applying a codingrule that there is a spectral null at one of a DC component and aNyquist component of a code spectrum and a partial-response class-IVinter-symbol-interference rule.

In the code detecting step, code detection may be performed using atrellis diagram to which the coding rule on the spectral null at the DCcomponent and the inter-symbol-interference rule for three bits areapplied.

The code may be a combination of codes in which the number ofconsecutive ones in a signal prior to Non Return to Zero Inverted (NRZI)modulation is limited to a finite value.

The code may be a combination of codes with a coding rate of 8/9 orgreater.

The code may be a non-interleaved code sequence.

In the code, at least one of a digital sum variation (DSV) of a runningdigital sum (RDS) and a DSV of an alternating digital sum (ADS) of acode sequence may be limited to a predetermined value n (n is an integergreater than or equal to 2). In order to generate 2n or moretransitional states, the code detecting step may include arithmeticsteps, the number of which is the same as the number of states.

A program recorded in a first recording medium and a first program ofthe present invention includes a code detecting step of performingtrellis code detection by applying a coding rule that there is aspectral null at one of a DC component and a Nyquist component of a codespectrum and a partial-response class-IV inter-symbol-interference rule.

A decoding apparatus of the present invention includes

a code detector for performing trellis code detection by applying acoding rule that there is a spectral null at one of a DC component and aNyquist component of a code spectrum and a partial-response class-IVinter-symbol-interference rule; and a decoder for decoding the codedetected by the code detector.

A decoding method, a program recorded in a second recording medium, anda second program of the present invention includes a code detecting stepof performing trellis code detection by applying a coding rule thatthere is a spectral null at one of a DC component and a Nyquistcomponent of a code spectrum and a partial-response class-IVinter-symbol-interference rule; and a decoding step of decoding the codedetected by the code detector.

According to a trellis detector, a trellis code detecting method, and aprogram of the present invention, a trellis code is detected by applyinga coding rule that there is a spectral null at one of a DC component anda Nyquist component of a code spectrum and a partial-response class-IVinter-symbol-interference rule.

According to a decoding apparatus, a decoding method, and a program ofthe present invention, a trellis code is detected by applying a codingrule that there is a spectral null at one of a DC component and aNyquist component of a code spectrum and a partial-response class-IVinter-symbol-interference rule, and the detected code is decoded.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of a general read/writeapparatus.

FIG. 2 is a block diagram showing the structure of a read/writeapparatus according to the present invention.

FIG. 3 is a block diagram showing the detailed structure of an encodershown in FIG. 2.

FIG. 4 is a block diagram showing the detailed structure of a codedetector shown in FIG. 2.

FIG. 5 is an illustration for describing an 8-state transition diagramused in the present invention.

FIG. 6 is an illustration for describing a 16-state trellis diagram usedin the present invention.

FIG. 7 is a block diagram showing the detailed structure of the codedetector shown in FIG. 4.

FIG. 8 is a block diagram showing the detailed structure of a 16-statetrellis code detector shown in FIG. 7.

FIG. 9 is a flowchart showing a decoding process.

FIG. 10 is a block diagram showing the structure of an interleavingencoder according to a comparative example.

FIG. 11 is a block diagram showing the structure of a de-interleavingcode detector according to the comparative example.

FIG. 12 is a block diagram for describing an 8-state trellis diagramused in the comparative example.

FIG. 13 is a block diagram showing the detailed structure of the codedetector shown in FIG. 11.

FIG. 14 is a block diagram showing the detailed structure of an 8-statetrellis code detector shown in FIG. 13.

FIG. 15 is a diagram for describing the relationship between the biterror rate and the signal-to-noise ratio of the code detector accordingto the present invention and the code detector according to thecomparative example.

FIG. 16 is a block diagram showing the structure of a personal computer.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter embodiments of the present invention will be described withreference to the drawings.

FIG. 2 is a block diagram of a digital signal processing circuitaccording to the present invention. The same reference numerals aregiven to portions corresponding to those in a known case, anddescriptions thereof are appropriately omitted (the same applies to thefollowing description). Specifically, the read/write apparatus shown inFIG. 2 includes an encoder 31 in place of the encoder 1 and a codedetector 32 in place of the code detector 6. Other than these, theread/write apparatus shown in FIG. 2 has a structure similar to that ofFIG. 1.

FIG. 3 is a block diagram showing an example of the detailed structureof the encoder 31.

The encoder 31 is a non-interleaving type. An m/n encoder 41 convertsm-bit input data into an n-bit write code at a time interval of nTs andinputs the n-bit write code to a parallel/serial converter 42, where Tsdenotes a system clock time interval. The parallel/serial converter 42converts the received write code into a 1-bit write code at a timeinterval of Ts and outputs the converted 1-bit write code to the A/Dconverter 2 shown in FIG. 2.

The structure of the encoder 31 described using FIG. 3 is a generalnon-interleaving encoding circuit used in modulation schemes other thanknown TCPR4 modulation. In other words, the read/write apparatusaccording to the present invention is characterized in that the encoder31 having a structure similar to that of the non-interleaving encodingcircuit is used to implement TCPR4 modulation. TCPR4 modulation refersto a modulation scheme combining trellis code modulation and an ISI rule(Inter-Symbol-Interference Rule) of (1−D²).

A write code output from the non-interleaving encoder 31 is converted bythe D/A converter 2 into a write rectangular wave, as in the casedescribed using FIG. 1, which in turn is recorded on a recording medium(not shown) by the read/write unit 3.

The signal recorded on the recording medium, which is read by theread/write unit 3, is equalized by the analog equalizer 4 topredetermined target equalization characteristics, as in the casedescribed using FIG. 1. The equalized signal is converted by the A/Dconverter 5 into a digital equalized signal that is quantized into abits, and the a-bit quantized digital equalized signal is output to thecode detector 32.

FIG. 4 is a block diagram showing an example of the detailed structureof the code detector 32.

The code detector 32 is a non-de-interleaving type. The a-bit quantizedequalized signal is converted by a code detector 51 into an n-bit code.In other words, a code is detected. The detected code is synchronized bya latch 52 and output to the decoder 7.

As shown in FIG. 4, the code detector 32 according to the presentinvention needs only one code detector 51. Such a structure is thestructure of a general non-de-interleaving code detecting circuit usedin modulation schemes other than known TCPR4 modulation. In other words,the read/write apparatus according to the present invention ischaracterized in that the code detector 32 having a structure similar tothat of the non-de-interleaving code detecting circuit, which is used inmodulation schemes other than known TCPR4 modulation, is used toimplement TCPR4 modulation.

The detected code output from the code detector 32 is decoded at a rateof n:m by the decoder 7, as in the case described using FIG. 1, and thedecoded code is output as output data.

Preferably, the DSV or A-DSV of the code used in the read/writeapparatus described using FIGS. 2 to 4 can be any value, though itshould be as small a value as possible in order to simplify the trelliscode detector. Both NRZ (Non-return to zero) modulation and NRZI (NonReturn to Zero Inverted (Non Return to Zero on one)) modulation areapplicable to the read/write apparatus. In this description, a 24/27conversion code for NRZI modulation with DSV=8 is used. In FIGS. 3 and4, the value of n is 27 (n=27).

FIG. 5 shows an 8-state transition diagram for code generation assumingNRZI modulation where the DSV of a code is limited to 8.

In the state transition diagram shown in FIG. 5, a 24/27 conversion codestarting in state 2 or 3 and ending in state 4 or 5 and a 24/27conversion code starting in state 4 or 5 and ending in state 2 or 3 arealternately used.

According to the state transition diagram, a sequence of the maximumnumber of 0 symbols is obtained when the state transits in the sequence7, 5, 3, 1, 2, 4, 6, and 8, wherein Tmax is 7T.

This coding method eliminates a possible code sequence based on which anestimated code cannot be determined by maximum likelihood codedetection, that is, QCS (Quasi-catastrophic sequence), and performsencoding/decoding by splitting a high coding rate 24/27 code into a12/13 conversion code and a 12/14 conversion code. The circuitry of theencoder and decoder thus only requires a few thousand gates, which is apractical circuit size.

The details of the coding method are disclosed by the inventor of thepresent invention in Japanese Unexamined Patent Application PublicationNo. 11-186917 and by M. Noda in “High-Rate Matched Spectral Null code,”IEEE Trans. on Magn., vol. 34, No. 4, pp. 1946–1948, July 1998. Thetechnology disclosed in these documents employs a bitwise interleavedcode. In contrast, the read/write apparatus according to the presentinvention employs, as described using FIG. 3, a non-interleaved code.Therefore, Tmax of the code is 7T.

FIG. 6 is a 16-state trellis diagram for 2 periods of time (2T) based ona channel clock, which is used in the code detector 51 of the codedetector 32 described using FIG. 4. Using the state transition diagramdescribed with reference to FIG. 5, when a code for use is interleavedon a bit-by-bit basis, the trellis diagram has 8 states, which will bedescribed below. In the read/write apparatus according to the presentinvention, no interleaving is performed. The trellis diagram thus has 16states.

In FIG. 6, each state colored white or black denotes the positive ornegative polarity of a write code after NRZI modulation. Each statedenoted by a circle or a square denotes the positive or negativepolarity of one previous bit of the write code after NRZI modulation.For one RDS value, a single state is allocated. The solid or dotted lineoutput from each state denotes that the code before NRZI modulation is 1or 0.

The trellis diagram shown in FIG. 6 takes into consideration alimitation rule of the DSV of the code and inter-symbol-interference forthree bits. The minimum squared Euclidean distance is 4. The trellisdiagram has a basic repeating unit per 2T. In the actual apparatus, thetrellis diagram is repeatedly used.

In FIG. 6, QCS is not eliminated. In actual use, part of the states ofthe trellis diagram is eliminated in accordance with the above-describedcode state transition rule, depending on the detection time.Accordingly, QCS is eliminated.

FIG. 7 is a block diagram showing an example of the detailed structureof the code detector 51 of the code detector 32 described using FIG. 4,which is designed to detect a code when the 24/27 conversion code forNRZI modulation with DSV=8 is used, that is, when the 16-state trellisdiagram described with reference to FIG. 6 is used.

The a-bit quantized equalized signal is separated into two lines, whichare input to a synchronization code detector 61 and a delay unit 62. Thesynchronization code detector 61 performs code detection using a generalViterbi detecting method involving obtaining a path with the minimummetric and performing maximum likelihood decoding in every state at eachpoint in the trellis diagram and outputs to a time counter 63 a 1-bitreset signal indicating whether or not a synchronization code isdetected.

The time counter 63 outputs 1 to 54 6-bit time information, which isreset in accordance with the reset signal input from the synchronizationcode detector 61, to a 16-state trellis code detector 64. The timecounter 63 counts up to 54, which is two times 27, i.e., the number ofbits after coding, because the code has been converted differently on abit-by-bit basis, as described above.

The delay unit 62 receives the a-bit quantized equalized signal inputand delays the equalized signal so that the phase of the equalizedsignal matches that of the reset signal output from the synchronizationcode detector 61. The delay unit 62 outputs a delayed a-bit equalizedsignal to the 16-state trellis code detector 64.

The 16-state trellis code detector 64 receives the delayed equalizedsignal and the time information, performs code detection, and outputs a27-bit detected code. FIG. 8 is a block diagram showing an example ofthe detailed structure of the 16-state trellis code detector 64.

The 6-bit time information input from the time counter 63 is input to asplitter 71 and a bus memory 73. The delayed a-bit equalized informationinput from the delay unit 62 is input to ACS (add, compare, and select)circuits 72-1 to 72-16.

Alternatively, branch metrics for metric calculation are calculated inadvance, and the branch metrics are input to the ACS circuits 72-1 to72-16.

On the basis of the input time information and the 16-state trellisdiagram described using FIG. 6, the splitter 71 generates 16 types of2-bit time-varying information indicating whether or not each path oftwo metrics input to each of the ACS circuits 72-1 to 72-16 is broken,selects two appropriate metrics from among 16 previous time metrics thatare quantized into b bits for each of the ACS circuits 72-1 to 72-16,and outputs the selected metrics to the ACS circuits 72-1 to 72-16. Inother words, the splitter 71 outputs a total of 16×(2b+2)-bitinformation.

The ACS circuits 72-1 to 72-16 all have the same circuit configuration.By performing the arithmetic processing for addition, comparison, andselection, each of the ACS circuits 72-1 to 72-16 feeds back the currenttime metric to the splitter 71 and outputs a 1-bit state addressindicating a surviving path to the bus memory 73.

The bus memory 73 that has received the input of the 1-bit stateaddresses selects the correct path on the basis of the addressinformation, the 6-bit time information input from the time counter 63,and the 16-state trellis diagram described using FIG. 6 and outputs a27-bit detected code with the maximum likelihood.

As described above, in the read/write apparatus described using FIGS. 2to 8, TCPR4 modulation is realized using the 16-state trellis diagramshown in FIG. 6 and applying non-interleaving and non-de-interleaving.Therefore, Tmax is not increased.

With reference to the flowchart of FIG. 9, a decoding process will nowbe described.

In step S1, the synchronization code detector 61 and the delay unit 62receive an input equalized signal that has been quantized into a bits.

In step S2, the synchronization code detector 61 performs code detectionusing a general Viterbi detecting method that involves obtaining a pathwith the minimum metric and performing maximum likelihood decoding inevery state at each point in the trellis diagram and outputs to the timecounter 63 a 1-bit reset signal indicating whether or not asynchronization code is detected.

In step S3, the time counter 63 outputs 1 to 54 6-bit time information,which is reset in accordance with the reset signal input from thesynchronization code detector 61, to the 16-state trellis code detector64. The time counter 63 outputs 1 to 54 6-bit time information, which isreset in accordance with the reset signal input from the synchronizationcode detector 61, to the 16-state trellis code detector 64. The timecounter 63 counts up to 54, which is two times 27, i.e., the number ofbits after coding, because the code has been converted differently on abit-by-bit basis.

In step S4, the delay unit 62 receives the a-bit quantized equalizedsignal, which is input in step S1, and delays the equalized signal sothat the phase of the equalized signal matches that of the reset signaloutput from the synchronization code detector 61. The delay unit 62outputs a delayed a-bit equalized signal to the 16-state trellis codedetector 64.

In step S5, the 16-state trellis code detector 64 receives the delayedequalized signal and the time information, as described using FIG. 8,performs code detection, and outputs a 27-bit detected code to the latch52.

In step S6, the latch 52 synchronizes the input detected code andoutputs the synchronized code to the decoder 7.

In step S7, the decoder 7 decodes the input detected code at a rate ofn:m and generates and outputs output data. The process is thuscompleted.

Using FIGS. 2 to 9, the TCPR4 non-interleaving and non-de-interleavingread/write apparatus according to the present invention has beendescribed. As a comparative example, a TCPR4 interleaving andde-interleaving read/write apparatus will now be described.

FIG. 10 is a block diagram showing an example of the structure of aninterleaving encoder used in the comparative example in place of theencoder 31 described using FIG. 3.

Input data of m bits is input to the m/n encoder 41 and converted intoan n-bit write code at a time interval of nTs. The n-bit code outputfrom the m/n encoder 41 is separated into two lines. One line is delayedby a latch 81 at a time interval of nTs, which in turn is delayed by alatch 82 at a time interval of 2nTs and output to a 1-bit interleaver84. The other line is delayed by a latch 83 at a time interval of 2nTsand output to the 1-bit interleaver 84.

The two lines of n-bit code are input to the 1-bit interleaver 84 andinterleaved on a bit-by-bit basis, which in turn is output to the D/Aconverter 2 described using FIG. 1.

The encoder with the structure described using FIG. 10 is a generallyused encoder when TCPR4 modulation is employed. In other words, in aknown read/write apparatus described using FIG. 1, the encoder 1 usedwhen TCPR4 modulation is employed has the structure described using FIG.10. The details of the encoder 1 are disclosed in, for example, anarticle by J. W. Rae, et al., IEEE Trans. on Magn., vol. 31, No. 2, pp.1208–1214, March 1995.

FIG. 11 is a block diagram showing an example of the structure of a codedetector used in the comparative example in place of the code detector32 described using FIG. 4.

An input a-bit equalized signal is input to an a-bit de-interleaver 91and de-interleaved into two lines. One of the two lines is input to acode detector 92-1, and the other is input to a code detector 92-2, bothof which are subjected to code detection at a time interval of 2nTs. Then-bit detected codes detected by the code detector 92-1 and the codedetector 92-2 are input to an n-bit interleaver 93 and interleavedn-bits by n-bits at a time interval of nTs, which in turn is output tothe decoder 7.

Hereinafter, when it is unnecessary to distinguish between the codedetector 92-1 and the code detector 92-2, they are generically referredto as the code detectors 92.

As described using FIG. 11, the two code detectors 92 are required todetect a code generated by interleaving. Each of the code detectors 92is a trellis detector for a dicode channel MSN code with 1−Dcharacteristics. Since the input equalized signal is subjected to codedetection while being de-interleaved bit by bit, the code detectorsshown in FIG. 11 together construct a detector circuit for a (1−D)² PR4channel MSN code.

The code detectors each having the structure described using FIG. 11 aregenerally used code detectors when TCPR4 modulation is employed. Inother words, in the known read/write apparatus described using FIG. 1,the code detector 6 used when TCPR4 modulation is employed has thestructure described using FIG. 11. As in the encoder with the structuredescribed using FIG. 10, the details of the code detector 6 aredisclosed in, for example, the article by J. W. Rae, et al., IEEE Trans.on Magn., vol. 31, No. 2, pp. 1208–1214, March 1995.

FIG. 12 is an 8-state trellis diagram for two periods of time, which isused by the code detectors 92 shown in FIG. 11.

Referring to FIG. 12, each state colored white or black denotes thepositive or negative polarity of a write code after NRZI modulation. Forone RDS value, a single state is allocated.

The trellis diagram shown in FIG. 12 takes into consideration alimitation rule of the DSV of the code and inter-symbol-interference fortwo bits. The minimum squared Euclidean distance is 4, which is similarto a case of the 16-state trellis diagram described using FIG. 6. As inthe case described using FIG. 6, the trellis diagram has a basicrepeating unit for two periods of time. In the actual apparatus, thetrellis diagram is repeatedly used.

In FIG. 12, QCS is not eliminated. In actual use, part of the states ofthe trellis diagram is eliminated in accordance with the above-describedcode state transition rule, depending on the detection time.Accordingly, QCS is eliminated.

FIG. 13 is a block diagram showing an example of the detailed structureof each of the code detectors 92 of the code detector described usingFIG. 11, which is designed to detect a code when the 8-state trellisdiagram described with reference to FIG. 12 is used.

The a-bit quantized equalized signal is input to a synchronization codedetector 101 and a delay unit 102. The synchronization code detector 101performs code detection using a general Viterbi detecting method andoutputs to a time counter 103 a 1-bit reset signal indicating whether ornot a synchronization code is detected.

The time counter 103 outputs 1 to 54 6-bit time information, which isreset in accordance with the reset signal input from the synchronizationcode detector 101, to an 8-state trellis code detector 104.

The delay unit 102 receives the a-bit quantized equalized signal inputand delays the equalized signal so that the phase of the equalizedsignal matches that of the reset signal output from the synchronizationcode detector 101. The delay unit 102 outputs a delayed a-bit quantizedequalized signal to the 8-state trellis code detector 104.

The 8-state trellis code detector 104 receives the delayed equalizedsignal and the time information, performs code detection, and outputs a27-bit detected code. FIG. 14 is a block diagram showing an example ofthe detailed structure of the 8-state trellis code detector 104.

The 6-bit time information input from the time counter 103 is input to asplitter 111 and a bus memory 113. The delayed a-bit equalizedinformation input from the delay unit 102 is input to ACS circuits 112-1to 112-8.

Alternatively, branch metrics for metric calculation are calculated inadvance, and the corresponding branch metrics are input to the ACScircuits 112-1 to 112-8.

On the basis of the input time information and the 8-state trellisdiagram described using FIG. 12, the splitter 111 generates 8 types of2-bit time-varying information indicating whether or not each path oftwo metrics input to each of the ACS circuits 112-1 to 112-8 is broken,selects two appropriate metrics from among 8 previous time metrics thatare quantized into b bits for each of the ACS circuits 112-1 to 112-8,and outputs the selected metrics to the ACS circuits 112-1 to 112-8. Inother words, the splitter 111 outputs a total of 8×(2b+2)-bitinformation.

The ACS circuits 112-1 to 112-8 all have the same circuit configuration.By performing the arithmetic processing for addition, comparison, andselection, each of the ACS circuits 112-1 to 112-8 feeds back thecurrent time metric to the splitter 111 and outputs a 1-bit stateaddress indicating a surviving path to the bus memory 113.

The bus memory 113 that has received the input of the 1-bit stateaddresses selects the correct path on the basis of the addressinformation, the 6-bit time information input from the time counter 103,and the 8-state trellis diagram described using FIG. 12 and outputs a27-bit detected code with the maximum likelihood.

The performance of the read/write apparatus according to the presentinvention, which has been described using FIGS. 2 to 8, will now becompared with the performance of the read/write apparatus in thecomparative example, which has been described using FIGS. 10 to 14.

Using both of the read/write apparatuses, one megabit random data wasencoded. On the corresponding resultant code, the read/write apparatusaccording to the present invention performed NRZI modulation, whichcorresponds to the 1/(1−D) processing, and then the 1−D² PR4equalization processing. The read/write apparatus in the comparativeexample performed interleaved NRZI modulation, which corresponds to the1/(1−D²) processing, and then 1−D² PR4 equalization processing. In bothcases, white noise was added.

The corresponding PR4 equalized signals are subjected to trellis codedetection using the code detector 32 according to the present invention,which has been described using FIGS. 4, 7, and 8, and using the codedetector described using FIGS. 11, 13, and 14. In both cases, the biterror rate was measured.

Referring to FIG. 15, the relationship between the signal-to-noise ratioand the bit error rate of each of the read/write apparatus according tothe present invention and the read/write apparatus in the comparativeexample will now be described.

In FIG. 15, the ordinate represents the bit error rate on a logarithmicscale, and the abscissa represents the signal-to-noise ratio. A graph ofblack points in the diagram represents the measurement result of theread/write apparatus according to the present invention. A graph ofwhite points in the diagram represents the measurement result of theread/write apparatus in the comparative example.

The signal-to-noise ratio according to the present invention is slightlyinferior (by approximately 0.1 dB) to that in the comparative example.The reason for this is estimated that, according to the presentinvention, compared with the comparative example, although the minimumsquared Euclidean distance is 4 in both cases, the error rate of theminimum squared Euclidean distance is slightly increased since thenumber of states is increased from 8 to 16. Since such an increase inthe error rate of the code detecting method according to the presentinvention is very slight, the error rate can be safely considered asapproximately equivalent to that in the comparative example. Therefore,there is no problem in actual use.

When the code detecting method according to the present invention isused, compared with the case of a known method that involvesinterleaving and de-interleaving, Tmax of a trellis code to be used isreduced from 2x to x, that is, reduced to half of that in the knownmethod, with almost no increase in the error rate. In this embodiment,since x=7T, Tmax of a trellis code to be used is reduced from 14T to 7T.

If the number of states of trellis detection is y in the known case, thenumber of states required in the present invention is 2y, which is twicethe number of states in the known case. On the other hand, the number oftrellis detectors is reduced from two to one. Therefore, the circuitsize required to perform trellis detection in both cases isapproximately proportional to 2y, making almost no difference in bothcases. In other words, the code detector 32 of the read/write apparatusaccording to the present invention can be realized with the size almostequivalent to that of the code detector in the comparative example. Inthis embodiment, since y=8, the number of states is 16 states. Thecircuit size required to perform trellis detection is equivalent to thatin the known case.

In the state transition diagram described using FIG. 5, assuming thatNRZI modulation is performed, inversion of all 0's and 1's of a coderesults in a state transition diagram that imposes a limitation ofA-DSV=8. According to the present invention, code detection may beperformed using such a code in which A-DSV is limited to a finite numberto generate a corresponding trellis diagram.

If either DSV or A-DSV is set to a finite value, the minimum squaredEuclidean distance in the trellis diagram for performing code detectionof the PR4 equalized signal is 4. Therefore, the code detector achievesan approximately equivalent bit error rate in both cases.

For example, a limitation of A-DSV=10 is imposed, and, as in thisembodiment, a 24/27 conversion code is separated into a 12/13 conversioncode and a 12/14 conversion code. This results in a PR4 channel trelliscode in which Tmax=8T and the maximum number of consecutive ones in NRZIdata is 9.

When the present invention is applied to trellis code detection thatperforms code detection utilizing a coding rule for likelihoodcalculation, partial response class IV equalization is performed on aread signal, and code detection is performed using a trellis diagramincluding both a coding rule on a spectral null at one of a DC componentand a Nyquist component of a code spectrum and aninter-symbol-interference rule for three bits.

Although a case has been described in which the trellis diagram for usein code detection has twice the number of states as the limitationnumber of DSV or A-DSV, the number of states can be any value greaterthan or equal to 2N where N denotes the limitation number.

As a code for use in the present invention, a code whose DSV is limitedis preferable to a code whose A-DSV is limited because limiting DSVeliminates a code with a run greater than DSV. Compared with a case inwhich a code whose A-DSV is limited to the same value as DSV, Tmax ofthe code is reduced to a smaller value.

In a phase locking method, such as that used in DVC (Digital VideoCassette recorder) systems, that is, a method involving integrationdetection of a read signal, performing PLL and 1−D² processing, andreading a PR4 equalized signal, it is similarly preferable to limit theDSV of a code to a finite value in order to achieve high quality of theintegral detection signal.

When the maximum number of consecutive zeroes in a read signal is notlimited to a finite value, the code detector 32 may generate a QCS, andphase locking may fail in PLL. The circuit operation of PLL may becomeunstable.

In contrast, when the present invention is applied to a case in which anon-interleaved code is recorded, setting both the maximum number ofconsecutive zeros and the maximum number of consecutive ones in NRZIdata to finite values enables setting the maximum number of consecutivezeroes in a PR4 equalized read signal to a finite value.

Limiting the maximum number of consecutive zeroes in NRZI data isequivalent to limiting Tmax to a finite value. In the above-described24/27 conversion code in which DSV=8, the maximum number of consecutiveones in NRZI data is limited to 15.

When code interleaving is performed as in the comparative example,limiting the maximum number of consecutive zeroes in non-interleavedNRZI data (prior to interleaving) enables limiting the maximum number ofconsecutive zeroes in a read signal. It is thus unnecessary to limit themaximum number of consecutive ones in NRZI data.

In the actual circuitry implementation, QCS is generally eliminated froma code in advance in order to prevent degradation of a code detectiongain when the memory length of the path memory 73 described using FIG. 8is limited to a finite value.

In this embodiment, in order to eliminate QCS other than consecutiveones in NRZI data upon code detection, a QCS elimination methoddisclosed in Japanese Unexamined Patent Application Publication No.11-186917 and M. Noda, “High-Rate Matched Spectral Null code,” IEEETrans. on Magn., vol. 34, No. 4, pp. 1946–1948, July 1998 is used.However, the method of eliminating QCS in a code for use in the presentinvention is not limited to the above-described method. Needless to say,QCS in a code can be eliminated using any method.

Another specific method of eliminating QCS in a code is disclosed in,for example, L. Fredrickson, et al., “Improved trellis-coding forpartial-response channels,” IEEE Trans. on Magn., vol. 31, No. 2, pp.1141–1148, March 1995.

When the coding rate is low, noise emphasis in the high frequency bandis increased by PR4 equalization, which in turn causes degradation oferror rate of a read signal. It is thus preferable that the coding rateof a trellis code according to the present invention be set to at least8/9 as high a value as possible.

As described above, when the trellis code detecting method for thepartial response class IV channel according to the present invention isused, the maximum magnetization reversal interval Tmax of a trellis codeto be used is reduced to half of that in the case of a known methodwhile having the error rate and the circuit size equivalent to those inthe case of the known method. In the actual read/write apparatus, areduction in the maximum magnetization reversal interval Tmax of a codereduces overwrite noise upon signal reading and writing and stabilizesPLL, which is of very high industrial value.

The above-described series of processes may be executed by software. Aprogram constructing the software is installed from a recording mediuminto a computer included in dedicated hardware or, for example, ageneral personal computer capable of performing various functions byinstalling therein various programs.

The recording medium is formed of, as shown in FIG. 16, packaged mediaincluding a magnetic disk 141, an optical disk 142, a magneto-opticaldisk 143, and/or a semiconductor memory 144, which are distributed toprovide users with the program and which have recorded therein theprogram. The magnetic disk 141 includes a flexible disk. The opticaldisk 142 includes a CD-ROM (Compact Disk-Read Only Memory) and a DVD(Digital Versatile Disk). The magneto-optical disk 143 includes an MD(Mini-Disk) (trademark).

Using FIG. 16, a personal computer 121 will now be described.

A CPU (Central Processing Unit) 131 receives, via an input/outputinterface 132 and an internal bus 133, signal inputs corresponding tovarious instructions input by a user using an input unit 134 and, via anetwork interface 140, control signal inputs sent from another personalcomputer and performs various processes based on the input signals. AROM (Read Only Memory) 135 stores basically fixed data of programs andarithmetic processing parameters used by the CPU 131. A RAM (RandomAccess Memory) 136 stores programs used upon execution by the CPU 131and parameters that accordingly change during the execution. The CPU131, the ROM 135, and the RAM 136 are connected to one another by theinternal bus 133.

The internal bus 133 is also connected to the input/output interface132. The input unit 134 includes, for example, a keyboard, a touch pad,a jog dial, and/or a mouse and is operated by the user to input variousinstructions to the CPU 131. A display unit 137 includes, for example, aCRT (Cathode Ray Tube) or an LCD (Liquid Crystal Display) and displaysvarious information in the form of text or an image.

An HDD (hard disk drive) 138 drives hard disks to read or write aprogram to be executed by the CPU 131 or information. In a drive 139, ifnecessary, the magnetic disk 141, the optical disk 142, themagneto-optical disk 143, and/or the semiconductor disk 144 are placedto exchange data.

The network interface 140 is connected by wire using predeterminedcables or wirelessly to another personal computer and/or variousapparatuses other than the personal computer to exchange data with theseapparatuses. The network interface 140 accesses a web server via theInternet to exchange information.

The input unit 134 to the network interface 140 are connected to the CPU131 via the input/output interface 132 and the internal bus 133.

In this specification, steps for writing a program recorded in arecording medium not only include time-series processing performed inaccordance with the described sequence but also include parallel orindividual processing, which may not necessarily be performed in timeseries.

The code detecting method of the present invention may be combined witha generally known noise whitening method, e.g., a noise predictor.

INDUSTRIAL APPLICABILITY

According to a trellis detector, a trellis code detecting method, and aprogram of the present invention, a trellis code is detected by applyinga coding rule that there is a spectral null at one of a DC component anda Nyquist component of a code spectrum and a partial response class IVinter-symbol-interference rule. While having the error rate and circuitsize approximately equal to those in a known case, the maximummagnetization reversal interval Tmax of a trellis code to be used isreduced to half of that in the known case.

According to a decoding apparatus, a decoding method, and a program ofthe present invention, a trellis code is detected by applying a codingrule that there is a spectral null at one of a DC component and aNyquist component of a code spectrum and a partial response class IVinter-symbol-interference rule, and the detected code is decoded. Whilehaving the error rate and circuit size approximately equal to those in aknown case, the maximum magnetization reversal interval Tmax of atrellis code to be used is reduced to half of that in the known case.Accordingly, overwrite noise upon signal reading and writing is reduced,and PLL is stabilized.

1. A trellis code detector for performing code detection by using acoding rule for likelihood calculation, comprising: means for outputtinga digital signal; a code detector for performing trellis code detectionon the digital signal, wherein the code detector simultaneously appliesa plurality of coding rules to detect a code including: applying acoding rule on a trellis diagram that there is a spectral null at one ofa DC component and a Nyquist component of a code spectrum; applying apartial-response class-IV inter-symbol-interference rule; and applyingan inter-symbol-interference rule for three bits on the trellis diagram.2. The trellis detector according to claim 1, wherein the code is acombination of codes in which the number of consecutive ones in a signalprior to Non Return to Zero Inverted (NRZI) modulation is limited to afinite value.
 3. The trellis detector according to claim 1, wherein thecode is a combination of codes with a coding rate of 8/9 or greater. 4.The trellis detector according to claim 1, wherein the code is anon-interleaved code sequence.
 5. The trellis detector according toclaim 1, wherein, in the code, at least one of a digital sum variation(DSV) of a running digital sum (RDS) and a DSV of an alternating digitalsum (ADS) of a code sequence is limited to a predetermined value n (n isan integer greater than or equal to 2), and wherein the code detectorhas 2n or more states and includes ACS circuits, the number of which isthe same as the number of states, in order to generate 2n or moretransitional states.
 6. A trellis code detecting method of performingcode detection by using a coding rule for likelihood calculation,comprising: performing trellis code detection by simultaneously applyinga plurality of code detecting rules to detect a code including: applyinga coding rule on a trellis diagram that there is a spectral null at oneof a DC component and a Nyquist component of a code spectrum; applying apartial-response class-IV inter-symbol-interference rule; and applyingan inter-symbol-interference rule for three bits on the trellis diagram.7. The trellis detecting method according to claim 6, wherein the codeis a combination of codes in which the number of consecutive ones in asignal prior to Non Return to Zero Inverted (NRZI) modulation is limitedto a finite value.
 8. The trellis detecting method according to claim 6,wherein the code is a combination of codes with a coding rate of 8/9 orgreater.
 9. The trellis detecting method according to claim 6, whereinthe code is a non-interleaved code sequence.
 10. The trellis detectingmethod according to claim 6, wherein, in the code, at least one of adigital sum variation (DSV) of a running digital sum (RDS) and a DSV ofan alternating digital sum (ADS) of a code sequence is limited to apredetermined value n (n is an integer greater than or equal to 2), andwherein, in order to generate 2n or more transitional states, the codedetecting step includes arithmetic steps, the number of which is thesame as the number of states.
 11. A recording medium having recordedtherein a computer-readable program for a trellis code detector forperforming code detection by using a coding rule for likelihoodcalculation, the program comprising: computer executable instructionsfor performing trellis code detection by simultaneously applying aplurality of code detecting rules to detect a code including: applying acoding rule on a trellis diagram that there is a spectral null at one ofa DC component and a Nyquist component of a code spectrum; applying apartial-response class-IV inter-symbol-interference rule; and applyingan inter-symbol-interference rule for three bits on the trellis diagram.12. A decoding apparatus for performing code detection by using a codingrule for likelihood calculation, comprising: a code detector forperforming trellis code detection, wherein the code detectorsimultaneously applies a plurality of coding rules to detect a codeincluding: applying a coding rule on a trellis diagram that there is aspectral null at one of a DC component and a Nyquist component of a codespectrum; applying a partial-response class-IV inter-symbol-interferencerule; applying an inter-symbol-interference rule for three bits on thetrellis diagram; and a decoder for decoding the code detected by thecode detector.
 13. A decoding method for a decoding apparatus forperforming code detection by using a coding rule for likelihoodcalculation, comprising: performing trellis code detection bysimultaneously applying a plurality of code detecting rules to detect acode including: applying a coding rule on a trellis diagram that thereis a spectral null at one of a DC component and a Nyquist component of acode spectrum; applying a partial-response class-IVinter-symbol-interference rule; applying an inter-symbol-interferencerule for three bits on the trellis diagram; and a decoding step ofdecoding the code detected by the code detector.
 14. A recording mediumhaving recorded therein a computer-readable program for a decodingapparatus for performing code detection by using a coding rule forlikelihood calculation, the program comprising: computer executableinstructions for performing trellis code detection by simultaneouslyapplying a plurality of code detecting rules to detect a code including:applying a coding rule on a trellis diagram that there is a spectralnull at one of a DC component and a Nyquist component of a codespectrum; applying a partial-response class-IV inter-symbol-interferencerule; and applying an inter-symbol-interference rule for three bits onthe trellis diagram; and a decoding step of decoding the code detectedby the code detector.